Broadcom

Actively Hiring

Design Engineer

Austin, United States

Full time

Role Overview

We are looking for an energetic and passionate design engineer to join our Central Engineering Group and be part of a memory subsystem design team responsible for the development of large memory blocks and subsystems.

About Broadcom

Broadcom is a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions.

Key Responsibilities

Architect and design memory subsystems
Implement RTL of subsystem designs
Place and route (physical design)
Design closure: timing, DRC, LVS, EM/IR, etc.
Gate netlist synthesis

Requirements & Eligibility

Minimum of 8 years of relevant experience
Bachelor in Electrical Engineering
Strong design skills
Ability to write and debug Verilog RTL code
Place and route expertise
Proficient in running STA, DRC, EM/IR tools, and attaining design closure
Ability to code in Python
Good understanding of synthesis tools and running synthesis

Required Skills & Tech

VerilogRTLSTADRCLVSEM/IRPythonAutomation Scripts